1. Field of the Invention
The present invention is related to a solid-state image capturing apparatus and an electronic information device, and more specifically to an improved version of an amplified solid-state image capturing apparatus whose pixel section includes an amplifying circuit and an electronic information device using the amplified solid-state image capturing apparatus therein.
2. Description of the Related Art
In general, an amplified solid-state image capturing apparatus includes a pixel array section, the pixel array section being two-dimensionally arranged with pixel sections (also simply referred to as pixels hereinafter), which have an amplifying function; and a scanning circuit positioned near the pixel array section.
As an example of such an amplified solid-state image capturing apparatus, an APS (Active Pixel Sensor) image sensor, which is configured with a CMOS circuit that is advantageous for pixels to integrate with a peripheral driving circuit and signal processing circuit, is known. Further, of all the APS image sensors, a four-transistor APS image sensor is becoming popular in recent years.
FIG. 4 is a diagram explaining a conventional four-transistor amplified solid-state image capturing apparatus, showing a circuit structure of an individual pixel (unit pixel) that constitutes the solid-state image capturing apparatus.
As shown in FIG. 4, a pixel 110, which constitutes the conventional solid-state image capturing apparatus, is configured with a light receiving section 101 for converting light to electrons; a transfer transistor 102 for transferring a signal charge generated in the light receiving section 101 to a signal charge accumulation section 103; an amplifying transistor 105 for amplifying the signal charge transferred to the signal charge accumulation section 103 to generate a corresponding signal voltage; a reset transistor 104 for resetting the signal charge accumulation section 103, or a gate of the amplifying transistor 105, to a power supply voltage Vd; and a selection transistor 106 for transferring an output of the amplifying transistor 105 to a readout signal wire 107. In the solid-state image capturing apparatus described above, a plurality of pixels of such a structure are arranged in two dimensions, or in a matrix. The readout signal wire 107 described above is provided for each pixel row and every selection transistor for pixels in each pixel row is connected to the corresponding readout signal line 107. In addition, each readout signal line 107 is connected to a corresponding one constant current source load 111. The constant current source load 111 is configured with a transistor which is connected between one end of the readout signal line 107 and a ground connection, and the gate of the transistor is set to a constant voltage Vc.
Herein, the light receiving section 101 is generally configured with a buried photodiode (photoelectric conversion element). In addition, the transfer transistor 102 described above is connected between the signal charge accumulation section 103, which accumulates signal charges from the light receiving section 101, and a cathode of the photodiode, and its gate is connected to a transfer gate selection wire 123. The signal charge accumulation section 103 is also referred to as a floating diffusion section (FD section) hereinafter. The transfer transistor 102 is turned on when the voltage level of the transfer gate selection wire 123 is at a high level and transfers a signal charge generated in a photodiode to the signal charge accumulation section 103.
Further, the reset transistor 104 is connected between the signal charge accumulation section 103 and a source of voltage (power supply voltage Vd), and its gate is connected to a reset signal line 122. When the voltage level of the reset signal line 122 is at a high level, the reset transistor 104 is turned on and resets an electric potential of the signal charge accumulation section 103 described above to the power supply voltage Vd. Further, the amplifying transistor 105 and the selection transistor 106 described above are connected in series between the source of voltage (power supply voltage Vd) and the readout signal line 107 described above. A gate of the amplifying transistor 105 on the side of the source of voltage is connected to the signal charge accumulation section 103 described above. In addition, a gate of the selection transistor 106 on the side of the readout signal line is connected to a selection signal line 121, and when the voltage level of the selection signal line is at a high level, the selection transistor 106 is turned on and selects the pixel so that a signal voltage of the corresponding pixel is read out by the readout signal line 107.
Next, an operation will be described.
In the light receiving section 101, a signal charge is generated by photoelectric conversion of an incident light, and the signal charge generated in the light receiving section 101 is transferred to the signal charge accumulation section (FD section) 103 by the transfer transistor 102. The signal charge accumulation section 103 is reset to the power supply voltage Vd by the reset transistor 104 before the signal charge is transferred from the light receiving section 101. Therefore, each electric potential of the signal charge accumulation section 103 is amplified by the amplifying transistor 105 after resetting and after transferring the signal charge, and the electric potential is read out by the readout signal line 107 through the selection transistor 106. At the same time, a current corresponding to the electric potential of the signal charge accumulation section 103 is supplied from the pixel 110 to the readout signal line 107, and the supplied current is discharged to the ground connection side through the constant current source load 111. Accordingly, a readout voltage, which corresponds to the current supplied by the pixel 110, is generated in the readout signal line 107 and the readout voltage is output to a circuit in a latter part, so that a pixel data of each pixel is obtained.
In such a CMOS image sensor, problems, such as the decrease of the amount of signal charges due to the scaling down of a photoelectric conversion device (i.e., photodiode) and the increase of noise due to miniaturization of an amplifying MOS transistor, arise as miniaturization of pixel pitch makes a progress from 2.2 μm to 1.75 μm. Therefore, it is more effective to decrease the number of transistors themselves to decrease the area occupied by the transistors and increase the size of the photoelectric conversion devices than the miniaturization of the size of transistors. As a method to accomplish this, a three-transistor pixel structure (3TR structure) is proposed where a unit pixel is configured with a photoelectric conversion device and three transistors.
FIG. 5 is a diagram explaining a unit pixel (also simply referred to as a pixel hereinafter) with a 3TR structure), showing a circuit structure of two unit pixels connected to one readout signal line.
For example, a pixel 210 with 3TR structure includes a light receiving section 201 configured with a photodiode (electric conversion element); a transfer transistor 202 connected between the light receiving section 201 and a signal charge accumulation section 203 for accumulating signal charges from the light receiving section 201; a reset transistor 204 connected between the signal charge accumulation section 203 and a reset drain wiring 225; and an amplifying transistor 205 connected between a source of voltage (power supply voltage Vd) and a readout signal line 207.
Herein, a transfer gate selection line 223 is connected to a gate of the transfer transistor 202 described above, and the transfer transistor 202 receives a transfer pulse signal TXO from the transfer gate selection line 223 to transfer a signal charge generated in the light receiving section 201 to the signal charge accumulation section 203. In addition, a reset signal line 222 is connected to a gate of the reset transistor 204, and the reset transistor 204 applies a voltage Vr0 of the reset drain wiring 225 to the signal charge accumulation section 203 in response to a reset signal RST0 from the reset signal line 222.
Similar to the pixel 210 with a 3TR structure described above, a pixel 250 with a 3TR structure is configured with a photodiode (electric conversion element), and the pixel 250 includes a light receiving section 251 for generating a signal charge by photoelectric conversion; a transfer transistor 252 for transferring the signal charge to a signal charge accumulation section 253 based on a transfer pulse signal TX1 from a transfer gate selecting line 273; a reset transistor 254 for applying a voltage Vr1 of a reset drain wiring 275 to the signal charge accumulation section 253 based on a reset signal RST1 from a reset signal line 272; and an amplifying transistor 255 for amplifying a signal voltage generated in the signal charge accumulation section 253 or a reset voltage and outputting the signal voltage or the reset voltage to the readout signal line 207.
The pixels 210 and 250, together with other pixels in the same row, are connected to the readout signal line 207, and the readout signal line 207 is connected to a constant current source load 211. The constant current source load 211 is constituted by a transistor that is connected between one end of the readout signal line 207 and a ground connection, and a gate of the transistor is set to a constant voltage Vc.
As shown in FIG. 5, the unit pixels 210 and 250 of such a 3TR structure, which differs from a unit pixel of a 4TR structure, is not provided with a transistor that corresponds to a selection transistor connected in series to the amplifying transistor 105 in FIG. 4. Therefore, a pixel selection operation for selecting a predetermined pixel from a plurality of pixels connected to the readout signal line 207 is not performed by a selection transistor in a 4TR structure but performed by controlling electric potentials of the FD sections 203 and 253, which are signal charge accumulation sections.
Next, an operation will be described.
FIG. 6 shows an example of a timing chart of a driving pulse that drives a unit pixel of a 3TR structure.
By controlling the transfer gate selection lines 223 and 273, the reset signal lines 222 and 272, and the reset drain wirings 225 and 275, the voltage of the FD sections 203 and 253 in each pixel are changed, and the voltage of the readout signal line 207 is also changed accordingly.
In the case where the pixel 210 is selected, for example, signal levels RST0 and RST1 of the reset gate wirings 222 and 272 rise after signal levels Vr0 and Vr1 of the reset drain lines 225 and 275 are set to low level electric potentials (VL), so that the electric potentials of the FD sections 203 and 253 are set to a low level (low reset).
Next, the constant current source load 211 of the readout signal line 207 that corresponds to a pixel row with the pixel 210 is operated by raising a gate control voltage Vc of a transistor that configures the constant current source load 211 (time t0). Subsequently, by changing the electric potential Vr0 of the reset drain wiring 222 connected to the selected pixel 210 to a high level (time t1), only an electric potential FD0 of the FD section 203 of the selected pixel 210 is changed to a high level (high reset). At this time, the voltage (VFD) of the FD section 203 is:VFD=Vd−Vth  (equation 1)
Herein, Vd is power supply voltage, and Vth is threshold voltage of the reset transistor 204. In this manner, the voltage VFD of the FD section 203 becomes smaller than the power supply voltage Vd, and therefore it is disadvantageous to complete charge transferring. As a solution, a transistor with low threshold voltage or a depletion-type transistor as the reset transistor 204 is used, so that the voltage of the FD section 203 at the time of high reset can be raised near the power supply voltage.
Next, if the signal level RST0 of the reset gate wiring 222 of the selected pixel 210 falls (time t2), the electric potential FD0 of the FD section 203 falls because of a coupled capacitance C1 between the gate of the reset transistor 204 and the FD section 203. Further, the change in the electric potential FD0 appears in the readout signal line 207 through the amplifying transistor 205, and therefore the voltage Vout of the readout signal line 207 also falls, and further, the voltage VD0 of the FD section 203 falls because of a coupled capacitance C2 between the readout signal line 207 and the gate of the amplifying transistor 205.
Due to the effect of the combining of these capacitances, the electric potential FD0 of the FD section 203 becomes smaller than the power supply voltage Vd. The signal line voltage (reset level) Vout corresponding to the voltage FD0 of the FD section 203 is taken in to a circuit in the next step (not shown) that is connected to the readout signal line 207.
Subsequently, when a transfer gate pulse (transfer pulse signal) TX0 is applied to the transfer transistor 202 (time t3 to t4), a signal charge is transferred from the light receiving section 201 to the FD section 203, so that the electric potential FD0 of the FD section 203 falls and the voltage level Vout of the readout signal line 207 simultaneously decreases. The voltage Vout of the readout signal line 207 is taken as a signal level Vsig into the circuit in the next step. The circuit in the next step takes the difference between the reset level Vrst and the signal level Vsig to output it as a pixel signal of the selected pixel 210.
After the signal level RST0 of the reset drain wiring 222 turns to be at a high level (time t5) and the electric potential FD0 of the FD section 203 turns to be at a high level, the signal level of the reset drain wiring 225 turns to be at a low level (time t6) and the electric potential of the FD section 203 turns to be at a low level. Then, the transistor 211 that configures the constant current source load turns to be off (time t7).
During such readout of a pixel signal from a selected pixel, the voltage level Vr1 of the reset drain wiring 275 of an unselected pixel 250 is at a low level and the signal level RST1 of the reset signal line 272 is at a high level. Therefore, the electric potential of the FD section 253 of the unselected pixel 250 is fixed to a low level, and the electric potential of the FD section 253 will not change even if the electric potential of the readout signal line 207 changes.
However, such a drive causes the voltage of the FD section 207 after resetting to decrease because of the coupled capacitance C1 between the gate of the reset transistor 204 and the FD section 203 as well as the coupled capacitance C2 between the readout signal line 207 and the gate of the amplifying transistor 205. Therefore, a problem arises that a complete transferring (no afterimage) cannot be performed because a sufficient electric potential is not secured between the photoelectric conversion element (light receiving section) 201 and the FD section 203 when the transfer transistor 202 is turned on.
Reference 1 discloses a method for raising the voltage of an electric potential of an FD section in a 3TR structure pixel as a solution for such a problem.
In the method described above, it is necessary to set the width of the reset pulse that resets the electric potential of the FD section shorter than the time for the readout signal line 207 to follow the reset voltage of the FD section 203.
That is, if the voltage Vr0 of the reset drain wiring 225 rises and the FD section 203 reaches a reset level and subsequently the signal level RST0 of the reset signal line 222 falls before the readout signal line 207 follows, the electric potential of the FD section 203 decreases because of the coupled capacitance C1 of the gate of the reset transistor. At this time, however, the readout signal line 207 is still on the way to rise, and therefore the voltage of the FD section 203 rises because of the coupled capacitance C2 between the FD section 203 and the readout signal line 207. Consequently, the reset level of the FD section can be set high without decreasing the electric potential of the FD section by the coupled capacitance.
The method disclosed in Reference 1 will be briefly explained using FIG. 7 where the method is applied for the operation of the pixel 210 shown in FIG. 5.
In the selected pixel 210 shown in FIG. 5, in a state where the signal level RST0 of the reset signal line 222 is at a high level and the reset transistor 204 is turned on, when the electric potential level Vr0 of the reset drain wiring 225 is at a high level (time t1) the amplifying transistor 205 is turned on and the charging by the power supply voltage Vd of the readout signal line 207 is performed. Next, if the signal level RST0 of the reset signal line 222 falls (time t2a) before the readout signal line 207 follows the power supply voltage Vd due to the charging, the decrease of the electric potential FD0 of the FD section 203 because of the coupled capacitance C1 between the gate of the reset transistor 204 and the FD section 203 is counteracted by the rise of the readout signal line 207 that is capacitively-coupled with the FD section 203. As a result, the electric potential level FD0 of the FD section 203 is maintained at or above the power supply voltage Vd.    Reference 1: Japanese Laid-Open Publication No. 2005-86595